This invention relates to apparatus for automatic testing of complex devices, and is particularly applicable to apparatus for automatic testing of complex electronic circuit devices. Such devices may be fabricated in a variety of technologies and over a wide range of integration scales.
In manufacture of electronic circuit devices, it is important to be able to verify that a particular unit meets the functional specifications prescribed for that model of circuit. Such an electronic circuit device is typically tested either manually, with discrete test and measurement instruments, or by using an automated test equipment (ATE) system if one with sufficient capability is available. Use of an automated test system is preferred over the manual method of testing for reasons of speed, accuracy and repeatability, but an automated test system often cannot provide adequate capabilities to perform all required tests for full and accurate device parameter verification.
An ATE system comprises a test socket that is mated with connection pins of the device under test (DUT), a stimulus device for applying a preset sequence of stimuli to the DUT and an acquisition device for receiving signals representative of the response of the DUT to the stimuli. Computer control of stimulus and acquisition instrumentation resources integrate the whole into a system that is instructed through software to perform complex testing processes.
In a conventional ATE system, the stimulus device and the acquisition device operate under timing control of a single master event controlling device which specifies the phase relationships between all activities in a given test procedure. In order to provide maximum accuracy while also providing minimum test time, Digital Signal Processing (DSP) techniques are employed for testing of analog parameters and relationships between analog (continuously variable) and digital (discretely variable) activities. The primary requirement for rapidly-executing DSP test techniques is coherent timing between stimulus and acquisition activities. Coherent timing requires precise integer ratios between frequencies of execution and renders absolute accuracy of the frequencies of much less importance. For this reason, a conventional coherent automated test system contains a single master timing reference from which all stimulus and acquisition device state timing is derived.
This timing approach allows many characteristics of the DUT to be measured, but is subject to some limitations. For example, the conventional coherent ATE system, having a single master event controlling device, is not well suited to testing certain device parameters. For example, an important figure-of-merit relative to an analog-to-digital converter (ADC) is the linearity of the quantization process utilized for the conversion of a continuously-variable analog signal to discrete values in an evenly spaced digital scale. The conversion linearity depends on the accuracy of the sampler portion of the ADC. Certain high-speed samplers employ a circuit configuration that is not stable for more than a short period of time after being placed into a known stable calibration state and released for operation. Such a sampler therefore requires repeated calibration. The ADC is placed in its calibration state by a discrete stimulus signal from an external source, typically a micro-controller that is controlling operation of the apparatus containing the ADC. Although the ADC is continuously sampling and producing output data, the output data produced during a calibration cycle is invalid. An ADC with an unstable sampler of this type exhibits an overall operating cycle composed of a calibration cycle followed by a conversion cycle, which may contain multiple sampling and quantizing cycles.
The conversion linearity of an ADC with an unstable sampler may depend on the duration of the calibration cycle and the interval between calibration cycles. This implies that in order to measure conversion linearity of such an ADC, the tester must include stimulus and acquisition devices that operate intermittently. The requirement of coherent timing forces the stimulus, acquisition and controlling devices of the ATE system to operate at differing frequencies of state alteration as their respective tasks are executed. This creates great difficulty for a single event master device to accurately control starting, stopping, pausing and resumption of the various device activities as a test procedure executes.
Unstable configuration ADC sampling circuits are typically employed in applications intended for very high speed operation with many bits of resolution, such as high performance video graphics for computer-aided design tools. The combination of both high conversion rate and fine resolution implies that a large amount of data must be acquired in order to provide sufficient data points to adequately measure parameters to an accuracy corresponding to that resolution. The required number of data points cannot be acquired at the operating rate of the ADC in the maximum period of time available between successive calibration cycles. Therefore, the test process is forced to be discontinuous, with data gathered over multiple active periods between calibration cycles.
Ideally, the acquisition device captures only data generated by the ADC under test during active periods between calibration cycles. Additionally, the resulting data record is ideally a single, continuous set of all data points with no redundancy and a seamless continuity so that subsequent DSP data reduction algorithms are simple and rapidly executing. This would require that the test process be interrupted and resumed in response to the periodic calibration cycles so that the resulting data record appears to be a single continuous acquisition.
A conventional ATE system exhibits difficulty in management of the phase between measurement discontinuities among the separate test resource devices so that an extended acquisition period is required to ensure that all data is captured through redundancy over a number of active periods of the ADC under test. As a result, it is necessary to eliminate from the data record any data acquired while the ADC was undergoing calibration, and this can lead to difficulty in accurately and rapidly measuring such parameters as the linearity of the conversion process due to extensive pre-processing of the data record before the ideal seamless, complete-without-redundancy data record is produced.
Further, the conventional ATE system is not well suited to testing of a more general set of devices composed of functional blocks that operate in different time domains. The ADC discussed above embodies at least three time domains (the analog input sourcing device, the digital controlling device and the digital output acquisition device). A typical video processing circuit might include an ADC that operates under control of a synchronization signal associated with the analog input, a digital processing circuit connected to a standard digital interface and a digital-to-analog converter (DAC) producing an analog representation of the processed input signal for output in accordance with a video display standard. The establishment of the specific timing requirements of these different time domains leads to difficulty in testing characteristics that involve more than one functional block.